1. Field of the Invention
The present invention relates to semiconductor devices and fabrication methods therefor. More particularly, the invention pertains to structures for proving electrical interconnections between electronic components and methods for forming such structures.
2. State of the Art
Semiconductor devices that include integrated circuits are produced by fabricating a plurality of substantially identical integrated circuit (IC) patterns on a semiconductor wafer. Each circuit pattern defines an integrated circuit of an individual semiconductor die. A plethora of processes is typically used to form the integrated circuits, including for example, doping, photolithography, layering, etching, laser ablation, metallization, oxidation, layer removal, wafer thinning/planarization, die singulation, testing (before and after singulation) and packaging. Inasmuch as the major goals of semiconductor manufacturers are increased performance and lower cost, considerations such as device density (with concomitant higher circuit speeds and reduced power requirements) and enhanced reliability have assumed a high priority. The proliferation of hand held apparatus such as cellular phones, global positioning satellite (GPS) units, entertainment devices, electronic cameras, personal digital assistants (PDAs), and the like has demanded electronic circuitry of ever-reduced size and enhanced capabilities.
Complex microelectronic devices may require hundreds, or even thousands, of input and output connections between electronic components. These connections may be area-arrayed, for example, on the active surface or back side of a semiconductor die for accommodating solder balls and/or spaced in a row or rows on the active surface, e.g., along the periphery thereof or in a central region thereof. Various prior art processes for producing interconnections between electronic components such as, for example, semiconductor dice and carrier substrates such as interposers and circuit boards use prefabricated arrays or rows of leads, discrete wire bonds, solder or other conductive bumps, tape automated bonding (TAB), edge connections, and combinations thereof.
In a wirebonding process, a semiconductor substrate such as a semiconductor die with bond pads is physically supported. A fine wire is fed through a capillary of a wire bonding tool, whereby one end of the wire at the distal end of the capillary head makes contact with a bond pad and is bonded thereto, typically using thermal or ultrasonic energy or a combination thereof. The capillary head is then moved to another location while wire is fed therefrom to a second pad or lead finger of another (or the same) substrate, the wire being bonded to the second location and then severed. The process is repeated for each bond pad of the semiconductor substrate, making interconnection very time-consuming and, as bond pad and lead sizes shrink, ever more prone to error.
In tape-automated bonding (TAB) methods, a dielectric tape, such as is made of polyimide carries an array of metallic leads on one surface thereof, the leads having ends which are exposed through one or more apertures formed in the tape. The opposing ends of the leads are bonded to bond pads of a die and terminal pads at the end of traces on a carrier substrate, typically by ultrasonic or thermocompression bonding, and the outer ends are connected to external circuitry. Ultrasonic bonding and thermocompression bonding generate heat which may damage the circuitry and, again, as bond pad and trace sizes shrink, defective bonding becomes more likely.
In addition to forming reliable connections between electrical components, a significant goal in the semiconductor industry is to perform as many of the manufacturing operations as possible on an entire wafer prior to die separation (singulation), in order to speed production, enhance yields to reduce production costs, and increase device uniformity and reliability.
One of the critical limitations in the production of microelectronic assemblies relates to electrical interconnection of an IC device to another apparatus such as an interposer, test carrier, circuit board, another IC device, or other substrate or higher-level packaging. For example, a test carrier for testing a semiconductor component such as a bare semiconductor die or a chip scale package often includes contacts for making temporary electrical connections with external contacts, such as bond pads or conductive bumps, on the semiconductor component being tested. The test carriers themselves are typically connected to a test board and associated test circuitry by conductive pins or pads.
An inner lead bond (ILB) pattern on the active surface of a semiconductor die may include contacts in the form of (typically aluminum or aluminum alloy) bond pads, which are very small, e.g., 100-200 μm square, very closely spaced or “pitched” (typically along or adjacent a center line of the die or along the periphery of the die in the X-Y plane). As a result, it may be difficult to connect the inner lead bond pads with terminal pads of another substrate. Thus, wire bonding may be difficult, as may probe testing or burn-in of the semiconductor device.
In addition, compressive force along the Z axis (perpendicular to the active surface of the semiconductor substrate) may be used to achieve the desired electrical contact during probe testing and burn-in. Such forces may result in lifting and separation of bond pads from the active surface, particularly if all of the bond pad surfaces do not lie in the same plane, so that some bond pads undergo greater force from a probe needle, pin or other contact than other, more recessed ones contacted by probe needles, pins or other contacts carried by the same contact head. A similar effect may result from thermal expansion and contraction of the bond pads and connectors during manufacture, testing and use. Furthermore, as commonly practiced, the aluminum bond pads are electroless plated with nickel; the plating process tends to pull and curl the pad edges away from the die.
To electrically connect another substrate to the small contacts in the ILB pattern, the bond pads of the ILB pattern may be redistributed to other locations on the active surface using a redistribution layer (RDL) comprising conductive traces extending from the bond pads to an outer lead bond (OLB) pattern that includes terminal pads which are typically about 240 μm square and more widely pitched. Thus, interconnection to another substrate may be made with much fewer defects. However, the formation of the RDL traces and terminal pads requires at least one extra step of fabrication to form the RDL traces and a passivating layer thereover, and adds time and material expenses to the overall manufacturing process.
A method for forming flexible interconnections is shown in U.S. patents to Fjelstad, i.e., U.S. Pat. No. 6,417,029 issued Jul. 9, 2002 and U.S. Pat. No. 6,774,317 issued Aug. 10, 2004. As shown in these references, a flexible support structure is attached to a conductive sheet. The conductive sheet is selectively removed by etching, leaving “cooling tower” shaped posts with coplanar tips relative to each other. Each post becomes an interconnection which may be wire-bonded to an underlying microelectronic device. Flexibility is given to the array of posts by the flexible support structure.
In U.S. Pat. No. 6,635,514 to Fjelstad, issued Oct. 21, 2003, a method for compliantly connecting bond pads of a first substrate to connectors of a second substrate is described. Connecting posts are formed of a conductive elastomeric material.
As shown in U.S. Pat. No. 6,828,669 issued Dec. 7, 2004 to Smith et al., flexible interconnection components between substrates comprise conductors bent into an S-shape which are attached in a non-aligned manner and the space therebetween filled with a pliant layer.
U.S. Pat. No. 6,791,169 issued Sep. 14, 2004 to Carson discloses an interconnect in which spring-like S-shaped conductive elements extend through an interposed layer of an anisotropic conductive material.
In U.S. Pat. No. 6,555,759, issued Apr. 29, 2003 to Tzanavaras et al., singular compliant conductive bumps are formed on metallized bond pads and surrounded by a supporting layer such as a polymer.
None of the cited prior art patents provides a method for forming an interconnect completely in the wafer stage, with determinable, controllable and known flexibility and with much reduced possibility of thermal mismatch-caused damage. Such an interconnect would be desirable to employ in the semiconductor industry to achieve the desired miniature size and density of electronic devices.
Efforts by the inventor to overcome the disadvantages of the prior art with respect to substrate-to-substrate interconnect systems which are compliant or flexible have led to apparatus and methods of the invention, several exemplary embodiments of which are summarized, described in detail, illustrated and claimed as follows: